Y
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
y2 F R U' R' S U' R U R' f' r U R' U' M r' F R F' M'
My choice
23 HTM · 20 STM · 23 QTM
rotation
<U,R,F,M,S>
SpeedCubeDB, 4 votes
R U' R' S R' F R f' R U' B U2 B' R'
15 HTM · 14 STM · 16 QTM
rotationless
<U,R,F,B,S>
SpeedCubeDB, 3 votes
y2 R U2 r' U2 F' R U' R' F R' F' R F U2 M'
16 HTM · 15 STM · 19 QTM
rotation
<U,R,F,M>
SpeedCubeDB, 1 votes
S' R U' R' S R' F R F' R U' B U2 B' R'
17 HTM · 15 STM · 18 QTM
rotationless
<U,R,F,B,S>
SpeedCubeDB, 1 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: L R' F2' U' L' U L U' L F L' U F2' R U2' L'. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.