V
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
U' F R' F' R U R U' R' f R f' U' r' U' R U M'
My choice
19 HTM · 18 STM · 19 QTM
rotationless
<U,R,F,M>
SpeedCubeDB, 2 votes
y2 R U' R' U' R2 y R' F' R U' R U R' U' R U' R' F'
17 HTM · 17 STM · 18 QTM
3-gen
rotation
<U,R,F>
SpeedCubeDB, 1 votes
U2 x' z' D R2 U F U2 F D F' U F R D' F2 R2 D'
16 HTM · 16 STM · 21 QTM
rotation
<U,R,F,D>
SpeedCubeDB, 0 votes
F R U R' U R U' R' U2 F2 r U r' F U F'
16 HTM · 16 STM · 18 QTM
3-gen
rotationless
<U,R,F>
SpeedCubeDB, 0 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: x' z' D R2' F2' D R' F' U' F D' F' U2' F' U' R2' D' z x U2'. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.