Z
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
y r U' M2 U r' U2 r U' M2 U r'
My choice
13 HTM · 11 STM · 18 QTM
3-gen
rotation
oh
<U,R,M>
SpeedCubeDB, 4 votes
R2 S' R2 U' S2 U' R2 S' R2
12 HTM · 9 STM · 18 QTM
3-gen
rotationless
<U,R,S>
SpeedCubeDB, 4 votes
r' U M2 U' r U2 r' U M2 U' r
13 HTM · 11 STM · 18 QTM
3-gen
rotationless
oh
<U,R,M>
SpeedCubeDB, 3 votes
y' l U' M2 U R' F2 R U' M2 U l'
13 HTM · 11 STM · 18 QTM
rotation
<U,R,F,L,M>
SpeedCubeDB, 1 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: r' U M2' U' r U2' r' U M2' U' r. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.