Ua
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
R' U' R U' M U R' U r U2 M U M'
My choice
16 HTM · 13 STM · 17 QTM
3-gen
rotationless
oh
<U,R,M>
SpeedCubeDB, 3 votes
y S U2 R' U' R U R U S' R U' R'
14 HTM · 12 STM · 15 QTM
3-gen
rotation
<U,R,S>
SpeedCubeDB, 2 votes
y2 L' U' L U' M' U L' U l U2 M' U M
16 HTM · 13 STM · 17 QTM
3-gen
rotation
<U,L,M>
SpeedCubeDB, 1 votes
y R U R' U' M' U R U' R' U M U2 M' U M
19 HTM · 15 STM · 20 QTM
3-gen
rotation
oh
<U,R,M>
SpeedCubeDB, 1 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: R U R' U M' U' R U' r' U2' M' U' M U. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.