Ja
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
y' R' U R2 F2 D r' U r D' F2 R2 U' R
My choice
13 HTM · 13 STM · 17 QTM
rotation
<U,R,F,D>
SpeedCubeDB, 1 votes
y R' U R2 F2 D r' U' r D' F2 R2 U' R
13 HTM · 13 STM · 17 QTM
rotation
<U,R,F,D>
SpeedCubeDB, 1 votes
y2 R' F2 R2 U2 R' F R U2 R2 F2 R2 U2 R' U' R U' R'
17 HTM · 17 STM · 25 QTM
3-gen
rotation
<U,R,F>
SpeedCubeDB, 0 votes
U2 F U R' U2 R2 U R2 U R U R' U' F' U F R F'
18 HTM · 18 STM · 22 QTM
3-gen
rotationless
<U,R,F>
SpeedCubeDB, 0 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: F R' F' U' F U R U' R' U' R2' U' R2' U2' R U' F' U2'. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.