Gd
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
y' R U R' U' R' F R F' R U2 R2 F R F' R U2 R'
My choice
17 HTM · 17 STM · 20 QTM
3-gen
rotation
<U,R,F>
SpeedCubeDB, 4 votes
U F R U' R2 D' r U' r' D R F R' F' R F'
16 HTM · 16 STM · 17 QTM
rotationless
<U,R,F,D>
SpeedCubeDB, 0 votes
y F' L' U L U' L' U' L F L' U2 L2 F' L' F L' U2 L
18 HTM · 18 STM · 21 QTM
3-gen
rotation
<U,F,L>
SpeedCubeDB, 0 votes
y F R U' R2 D' r U' r' D R F R' F' R F'
15 HTM · 15 STM · 16 QTM
rotation
<U,R,F,D>
SpeedCubeDB, 0 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: F R' F R F' R' D' r U r' D R2' U R' F' U'. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.