E
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
R2 U2 R2 U' R2 U' R' U2 R' F R' F' R2 U R' U R' F R F'
My choice
20 HTM · 20 STM · 26 QTM
3-gen
rotationless
<U,R,F>
SpeedCubeDB, 3 votes
r' U r S' U f r' F' R U R' U' R' F r F'
17 HTM · 16 STM · 17 QTM
rotationless
<U,R,F,S>
SpeedCubeDB, 2 votes
R' F R U2 r U' r' U2 F' U2 r U R' U' M
16 HTM · 15 STM · 19 QTM
rotationless
<U,R,F,M>
SpeedCubeDB, 1 votes
R2 D R' U R D' R2 B' U' R' F U R U' F' U f
17 HTM · 17 STM · 19 QTM
rotationless
<U,R,F,D,B>
SpeedCubeDB, 1 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: M' U R U' r' U2' F U2' r U r' U2' R' F' R. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.