Aa
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
r R2 U r' F2 R F' r' F2 r2 U' M
My choice
13 HTM · 12 STM · 17 QTM
rotationless
<U,R,F,M>
SpeedCubeDB, 4 votes
y2 R U' R2 D' r U r' D R2 U' R' U' R U R' U' R U' R'
19 HTM · 19 STM · 21 QTM
3-gen
rotation
<U,R,D>
SpeedCubeDB, 2 votes
L' U' L U' L' U L U' L' U' L2 D l' U l D' L2 U' L
19 HTM · 19 STM · 21 QTM
3-gen
rotationless
<U,D,L>
SpeedCubeDB, 0 votes
M' R' U L' U2 R U' r' U2 r L U' M
15 HTM · 13 STM · 17 QTM
rotationless
<U,R,L,M>
SpeedCubeDB, 0 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: M' U L' r' U2' r U R' U2' L U' R M. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.