Cb

Parity PLL
A top-layer case that is not one of the PLLs: a lone swap, or a swap with a cycle.
Your status
Recognition & spaced review

Algorithms (1)

/3,0/1,0/4,0/5,0/4,0/0,-1/-2,1/2,0/-1,0/-3,0/0,-1/-3,0/3,0/0,-1
My choice
29 HTM · 29 STM · 49 QTM
3-gen
rotationless
</,U,D>
SpeedCubeDB, 0 votes

How this case is verified

The case is the source's setup (or, where it has none, another source algorithm reversed). Setup: (-3,-5) (0,1) / (-3,0) / (3,0) / (0,1) / (3,0) / (1,0) / (-2,0) / (2,-1) / (0,1) / (-4,0) / (-5,0) / (-4,0) / (-1,0) / (-3,0) /. Every algorithm above was run by our logic engine from that state and reaches "solved-up-to-layers".
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