WV 16
WV
With the pair ready for R U R', look at which way each last-layer corner's top colour faces.
Your status
Algorithms (4)
U R' D' R U R' D R2 U2 R'
My choice
10 HTM · 10 STM · 12 QTM
3-gen
rotationless
<U,R,D>
SpeedCubeDB, 4 votes
U2 R U' R' U' R' F R U R U' R' F'
13 HTM · 13 STM · 14 QTM
3-gen
rotationless
<U,R,F>
SpeedCubeDB, 3 votes
U R U' R' U' R2 D' R U2 R' D R U2 R
14 HTM · 14 STM · 17 QTM
3-gen
rotationless
<U,R,D>
SpeedCubeDB, 1 votes
U2 L' R U R' U' L R U2 R'
10 HTM · 10 STM · 12 QTM
3-gen
rotationless
<U,R,L>
SpeedCubeDB, 0 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: R U2' R2' D' R U' R' D R U'. Every algorithm above was run by our logic engine from that state and reaches "f2l-oll".