Pure
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
M' U2 M U2 M' U' M U2 M' U2 M U
My choice
18 HTM · 12 STM · 22 QTM
2-gen
rotationless
oh
<U,M>
SpeedCubeDB, 7 votes
M' U2 M U2 M' U' M U2 M' U2 M
17 HTM · 11 STM · 21 QTM
2-gen
rotationless
oh
<U,M>
SpeedCubeDB, 4 votes
M' U' M' U' M' U' M' U' M U' M U' M U' M U'
24 HTM · 16 STM · 24 QTM
2-gen
rotationless
oh
<U,M>
SpeedCubeDB, 2 votes
M' U' M' U' M' U' M' U M' U' M' U' M' U' M' U
24 HTM · 16 STM · 24 QTM
2-gen
rotationless
oh
<U,M>
SpeedCubeDB, 2 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: U' M' U2' M U2' M' U M U2' M' U2' M. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.