Na
Anti-PLL
Every top edge shows its side colour on top; read the permutation from the top stickers as for PLL.
Your status
Algorithms (4)
R2 U2 R' U2 F' U2 F f R2 f' U2 R U2 R2
My choice
14 HTM · 14 STM · 22 QTM
3-gen
rotationless
<U,R,F>
SpeedCubeDB, 1 votes
L' F U2 L2 F L' F2 L F' L2 U2 F' L
13 HTM · 13 STM · 18 QTM
3-gen
rotationless
<U,F,L>
SpeedCubeDB, 0 votes
F R U' R' U' R U R' F' U' F R U R' U' R' F' r U R U' r'
22 HTM · 22 STM · 22 QTM
3-gen
rotationless
<U,R,F>
SpeedCubeDB, 0 votes
L' B L2 D2 B l' U2 l B' D2 L2 B' L
13 HTM · 13 STM · 18 QTM
rotationless
<U,D,L,B>
SpeedCubeDB, 0 votes
How this case is verified
The case is the source's setup, checked against the source's case image. Setup: L' F U2' L2' F L' F2' L F' L2' U2' F' L. Every algorithm above was run by our logic engine from that state and reaches "pll-solved", keeping f2l.